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doc/parva/assembly_0.1.md
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doc/parva/assembly_0.1.md
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; LBP 24-bit CPU assembly version 0.1
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# Registers
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0000 | x0/ra | caller
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0001 | x1/sp | callee
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0010 | x2/bp | caller
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0011 | x3/s0 | callee
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0100 | x4/t0 | caller
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0101 | x5/t1 | caller
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0110 | x6/a0 | caller
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0111 | x7/a1 | caller
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; Read-only registers
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1000 | zero
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1001 | pc
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1010 | cycle
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1011 | upper (0xFFF000)
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1100 | (unused, may trigger different instruction)
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1101 | (unused, may trigger different instruction)
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1110 | (unused, may trigger different instruction)
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1111 | (unused, may trigger different instruction)
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; Double aliases
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000 | x01 | x0 + x1
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010 | x23 | x2 + x3
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100 | x45 | x4 + x5
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110 | x67 | x6 + x7
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# Encoding
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Instructions are fixed-width and 24 bits long. The following layouts are used:
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[ 5, opcode ] [ 4, source register A ] [ 3, dest register ] [ 3, source register B ] [ 9, padding ]
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[ 5, opcode ] [ 4, source register A ] [ 3, dest register ] [ 12, unsigned immediate ]
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[ 5, opcode ] [ 4, source register A ] [ 3, dest register ] [ 12, signed immediate ]
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[ 4, opcode ] [ 1, source register A ] [ 2, ones ] [ 2, source register A ] [ 3, dest register ] [ 12, signed immediate ]
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Depending on the instruction, the role of the registers may be swapped around.
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# ALU instructions (0)
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; addi/subi/mulu/mulhu immediate values are signed and will be sign-extended, others are unsigned
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; TODO: Don't sign-extend certain immediates
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; AAAA must be between 0000 and 1011, higher values may change the instruction
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00000 AAAA DDD IIIIII IIIIII | addi xA, xD, I
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00001 AAAA DDD BBB000 000000 | add xA, xD, xB
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00010 1000 DDD IIIIII IIIIII | lui xD, I ; load I into the upper 12 bits of xD
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00011 AAAA DDD BBB000 000000 | sub xA, xD, xB
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00100 AAAA DDD IIIIII IIIIII | slli xA, xD, I
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00101 AAAA DDD BBB000 000000 | sll xA, xD, xB
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00110 AAAA DDD IIIIII IIIIII | srli xA, xD, I
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00111 AAAA DDD BBB000 000000 | srl xA, xD, xB
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01000 AAAA DDD IIIIII IIIIII | srai xA, xD, I
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01001 AAAA DDD BBB000 000000 | sra xA, xD, xB
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01010 AAAA DDD IIIIII IIIIII | xori xA, xD, I
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01011 AAAA DDD BBB000 000000 | xor xA, xD, xB
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01010 AAAA DDD IIIIII IIIIII | ori xA, xD, I
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01011 AAAA DDD BBB000 000000 | or xA, xD, xB
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01110 AAAA DDD IIIIII IIIIII | andi xA, xD, I
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01111 AAAA DDD BBB000 000000 | and xA, xD, xB
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000A0 11AA DDD IIIIII IIIIII | mului xA, xD, I ; unsigned multiply, lower 24 bits of result
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000A1 11AA DDD BBB000 000000 | mulu xA, xD, xB
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001A0 11AA DDD IIIIII IIIIII | mulhu xA, xD, I ; unsigned multiply, upper 24 bits of result
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001A1 11AA DDD BBB000 000000 | mulhui xA, xD, xB
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010A0 11AA DDD IIIIII IIIIII | divui xA, xD, I ; unsigned integer divide, quotient
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010A1 11AA DDD BBB000 000000 | divu xA, xD, xB
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011A0 11AA DDD IIIIII IIIIII | remui xA, xD, I ; unsigned integer divide, remainder
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011A1 11AA DDD BBB000 000000 | remu xA, xD, xB
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; Pseudo-instructions
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nop => addi x0, x0, 0
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li xD, I => addi zero, xD, I
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lli xD, I => or xD, zero, I
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la xD, I => addi pc, xD, I
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li xD, imm24 =>
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lui xD, imm24[23:12]
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ori xD, xD, imm24[11:0]
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rdcycle xD => addi xD, cycle, 0
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mv xD, xA => addi xD, xA, 0
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not xD, xA =>
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xor xD, upper, xA
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xori xD, xA, -1
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# Data instructions (10)
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; lli and lui immediates are unsigned, other instruction immediates are signed
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; When loading/storing doubles, addresses must be a multiple of 2
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10000 AAAA DDD IIIIII IIIIII | lw xD, I(xA) ; load word at [xA + I] into xD
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10010 AAAA DDD IIIIII IIIIII | sw xD, I(xA) ; store xD into address [xA + I]
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10100 AAAA DDD IIIIII IIIIII | ld xDD, I(xA) ; load double [xA + I] into xDD
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10110 AAAA DDD IIIIII IIIIII | sd xDD, I(xA) ; store xDD into address [xA + I]
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; Not implemented
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10001 AAAA DDD BBB000 000000 | lw xD, xB(xA) ; load word at [xA + xB] into xD
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10011 AAAA DDD BBB000 000000 | sw xD, xB(xA) ; store xD into address [xA + xB]
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10101 AAAA DDD BBB000 000000 | ld xDD, xB(xA) ; load double [xA + xB] into xDD
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10111 AAAA DDD BBB000 000000 | sd xDD, xB(xA) ; store xDD into address [xA + xB]
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; Pseudo-instructions
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lw/sw/ld/sd xD, I => lw/sw/ld/sd xD, I(zero)
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# Memory-mapped I/O
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; Memory addresses after 0xFFF000 represent I/O and special registers. The next bit after 0xFFF is always 0, and the following 2 bits specify the device.
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; E.g. the memory range 0xFFF400 to 0xFFF5FF accesses I/O device 2
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; The read-only register "upper" (1011) can be used to generate I/O addresses easily.
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; E.g. sw x0, 0x205(upper)
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; To execute commands or set I/O device memory, write to a device address.
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; Commands with no arguments can be executed by writing `zero`.
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; Commands with one argument can be executed by writing a word.
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; Commands with two arguments can be executed by writing a doubleword.
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; Each I/O device has an associated input buffer which it can write to.
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; To pull data from this buffer, read from address 0 for the device.
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; Standard device memory ranges and immediate aliases
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111111 111111 000XXX XXXXXX | csr | special registers
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111111 111111 001XXX XXXXXX | kb | keyboard
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111111 111111 010XXX XXXXXX | gpu | GPU
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111111 111111 011XXX XXXXXX | snd | sound card
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; Special registers
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write | 0xFFF 000000 000000 | | request current clock time
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write | 0xFFF 000001 000000 | | request current clock time
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read | get requested value
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; Keyboard commands
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read | get keycode (bottom 12 bits) and modifiers (upper 12 bits), 0 if nothing pressed
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; GPU commands (TODO)
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write | 0xFFF 0111II IIIIII | A, B | write doubleword AB to VRAM address I
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write | 0xFFF 010001 000000 | A, B | move cursor to X position A and Y position B
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write | 0xFFF 010010 IIIIII | A | set character shape to A (0=6x8, 1=6x1)
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write | 0xFFF 010011 IIIIII | A | set current group to A
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write | 0xFFF 010100 000000 | A, B | print character to buffer with pixel values AB
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write | 0xFFF 010101 000000 | A | print character to buffer with pixel values at VRAM address [A]
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write | 0xFFF 010110 000000 | A, B | print character to screen with pixel values AB
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write | 0xFFF 010111 000000 | A | print character to screen with pixel values at VRAM address [A]
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write | 0xFFF 010000 000000 | | clear buffer of current group
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write | 0xFFF 010001 000000 | | clear current group on screen
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write | 0xFFF 010010 000000 | | print buffer of current group to screen
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write | 0xFFF 010011 000000 | | clear current group on screen and print its buffer
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write | 0xFFF 010100 000000 | | clear buffer of all groups
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write | 0xFFF 010101 000000 | | clear screen
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write | 0xFFF 010110 000000 | | print buffer of all groups to screen
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write | 0xFFF 010111 000000 | | clear screen and print buffer of all groups
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read | (not used)
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; Temporary simplified GPU commands
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010000 000000 | A, B | move cursor to X position A and Y position B
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010001 000000 | A | print 6x1 pixels A to buffer
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010010 000000 | A, B | print 6x8 pixels AB to buffer
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010011 000000 | | print buffer to screen
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010100 000000 | | clear screen
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010101 000000 | | clear screen and print buffer to screen
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; Sound card commands
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write | 0xFFF 011000 000000 | A | play beep with pitch A
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; Pseudo-instructions
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iolw xD, V => lw xD, (V << 9)(upper) ; read from input buffer for I/O device V into xD
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iosw xD, V, I => sw xD, (V << 9 + I)(upper) ; execute command I of device V with word argument xD
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iosd xDD, V, I => sd xDD, (V << 9 + I)(upper) ; execute command I of device V with double argument xDD
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# Branching instructions (11)
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; Branch (b) immediates are signed, jump (j) immediates are unsigned
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; Branching is relative, jumping is absolute
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; AAAA must be between 0000 and 1011
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11CCC AAAA DDD IIIIII IIIIII | bC xA, xD, I ; compare xA and xD for condition C and branch to [pc + I]
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11110 AAAA 000 IIIIII IIIIII | blt xA, zero, I
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11111 AAAA 000 IIIIII IIIIII | bge xA, zero, I
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11110 AAAA 100 IIIIII IIIIII | j I(xA) ; jump to [xA + I]
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11111 AAAA 100 BBB000 000000 | j xB(xA) ; jump to [xA + xB]
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; Conditions (C)
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000 | beq, equals
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010 | bltu, less than unsigned
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100 | blt, less than
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110 | blt, less than (with special operand)
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001 | bne, not equals
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011 | bgeu, greater than or equal unsigned
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101 | bge, greater than or equal
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111 | bge, greater than or equal (with special operand)
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beq: Z==1
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bne: Z==0
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blt: N!=V
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bltu: C==0
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bge: N==V
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bgeu: C==1
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; Pseudo-instructions
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b I => beq x0, x0, I
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b xB => j xB(pc)
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j xB => j xB(zero)
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wfi => beq x0, x0, 0
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bgt xD, xA, I => blt xA, xD, I
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bgtu xD, xA, I => bltu xA, xD, I
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ble xD, xA, I => bge xA, xD, I
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bleu xD, xA, I => bgeu xA, xD, I
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beqz xD, I => beq zero, xD, I
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bltz xD, I => blt xD, zero, I
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bnez xD, I => bne zero, xD, I
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bgez xD, I => bge xD, zero, I
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bgtz xD, I => blt zero, xD, I
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blez xD, I => bge zero, xD, I
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# Microcode
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; Channels
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i24 | alu_a: ALU input value A
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i24 | alu_b: ALU input value B
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b4 | ins_a: instruction operand A
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b3 | ins_d: instruction operand D
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b3 | ins_b: instruction operand B
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i12 | imm: instruction immediate value
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i24 | mout_a: memory write value a
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i24 | mout_b: memory write value b
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i24 | b_offset: branching offset
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